The present invention relates to a method of and apparatus for detecting a frequency drift of a value exceeding a specified value with respect to a reference clock in a Phase Locked Loop (PLL), and issuing an alarm when the detected frequency drift is higher than a specified value.
The conventional technology of this field will be explained below. FIG. 9 is a diagram showing a configuration of a PLL disclosed in xe2x80x9cTiming extraction/identification/reproduction IC for 2.5 Gbit/s optical transmissionxe2x80x9d by Akashi et al., 1998 General Conference of IEICE, Spring C-12-61. In FIG. 9, the legend 101 represents a first phase comparator (PD), 102 represents a second phase comparator (PD), 103 represents a frequency comparator (FD), 104 represents a selector (SEL), 105 represents a low-pass filter (LPF), 106 represents a step out detector, and 107 represents a voltage controlled oscillator (VCO) that outputs a first extracted clock (VCOCLK (1)) and a second extracted clock (VCOCLK (2)) whose phase lags a phase of the first extracted clock by 90 degrees. The first phase comparator 101, second phase comparator 102, frequency comparator 103, and the selector 104 constitute a phase frequency comparison section 111.
The operation of the phase frequency comparison section 111 and the operation of the overall PLL will be explained below. The first phase comparator 101 detects a phase difference between an input signal (DATA or CLK) and the first extracted clock. Likewise, the second phase comparator 102 detects a phase difference between the input signal and the second extracted clock.
As shown in FIG. 10, each of the phase comparators 101 and 102 is composed of a mixer (MIX) 112 and a low-pass filter (LPF) 113. If we let the input signal be sin (xcfx89CLKt+xcex1) and the first extracted clock be sin (xcfx89VCOCLK(1)t+xcex2), a signal output from the mixer 112 in the first phase comparator 101 is obtained as follows:
sin{(xcfx89CLKxe2x88x92xcfx89VCOCLK(1))t+(xcex1xe2x88x92xcex2)}xc3x97sin{(xcfx89CLK+xcfx89VCOCLK(1))t+(xcex1+xcex2)}xe2x80x83xe2x80x83(1)
That is, the signal output from the mixer 112 has a frequency component which is a sum and a difference between the two signals. In the expression (1), xcfx89CLK represents an angular frequency of the input signal, t represents a time, xcex1 represents a phase of the input signal, xcfx89VCOCLK(1) represents an angular frequency of the first extracted clock, and xcex2 represents a phase of the first extracted clock.
The low-pass filter 113 removes the sum component from the signal output from the mixer 112. Accordingly, the output signal of the first phase comparator 101 is obtained as follows:
sin{(xcfx89CLKxe2x88x92xcfx89VCOCLK(1))t+(xcex1xe2x88x92xcex2)}xe2x80x83xe2x80x83(2)
which can be expressed by a difference component between frequencies of the input signal and the first extracted clock.
On the other hand, in the second phase comparator 102, the second extracted clock becomes sin (xcfx89VCOCLK(1)t+xcex2+xcfx80/2), therefore, an output signal is obtained as follows:
sin{(xcfx89CLKxe2x88x92xcfx89VCOCLK(1))t+(xcex1xe2x88x92xcex2)xe2x88x92xcfx80/2}=xe2x88x92cos{(xcfx89CLKxe2x88x92xcfx89VCOCLK(1))t+(xcex1xe2x88x92xcex2)}xe2x80x83xe2x80x83(3)
As explained above, each of the two phase comparators outputs a beat waveform signal having the component showing the difference between frequencies (xcfx89CLKxe2x88x92xcfx89VCOCLK(1)) of the input signal and each of the extracted clocks.
For example, the output characteristic of each of the phase comparators 101 and 102, when frequencies are synchronous, can be expressed as shown in FIGS. 11A and 11B by substituting xcfx89CLKxe2x88x92xcfx89VCOCLK(1)=0 into the expressions (2) and (3). When a phase difference xcfx86(xcfx86=xcex1xe2x88x92xcex2) is xc2x1xcfx80/2 or less, the output of the first phase comparator 101 changes to a linear operation with respect to the phase difference particularly around zero. At this time, the level of the output of the second phase comparator 102 is fixed to LOW. Further, when the phase difference becomes xc2x1xcfx80/2 or more, the level of the output of the second phase comparator 102 changes in the linear region to be fixed to HIGH.
Each phase relationship between the output beat waveforms of the phase comparators 101 and 102, when the frequencies are asynchronous, can be expressed as shown in FIGS. 12A and 12B depending upon a magnitude relationship between frequencies of the input signal and the extracted clock, respectively. The frequency comparator 103 having received these two beat waveforms detects a phase relationship between the beat waveforms, and outputs binary signals indicating the high and low frequencies. The frequency comparator 103 is composed of, for example, a D type flip-flop. That is, by using a rising edge type of D type flip-flop, when receiving the output beat waveform of the first phase comparator 101 to a data terminal and receiving the output beat waveform of the second phase comparator 102 to a clock terminal, the frequency comparator 103 outputs a HIGH signal when the frequency of the input signal is high and outputs a LOW signal when it is low, that is, the frequency comparator 103 outputs binary digital signals indicating the high and low frequencies.
Output of the second phase comparator 102 is input to the selector 104 as a select signal through the step out detector 106. The step out detector 106 converts an analog input to a digital output by saturating an analog beat waveform having a linear region.
The selector 104 selects the output of the frequency comparator 103 when the select signal is HIGH, and selects the output of the first phase comparator 101 when the select signal is LOW. When the output of the second phase comparator 102 is HIGH, that is, when a phase difference is xc2x1xcfx80/2 or more, the output of the frequency comparator 103 is selected. The binary signal is then input to the voltage controlled oscillator 107 through the low-pass filter 105, and the frequency of the extracted clock approaches the frequency of the input signal at a high speed. When the frequencies of the extracted clock and the input signal coincide with each other and the phase difference becomes xc2x1xcfx80/2 or less (the output of the second phase comparator 102 is LOW), the selector 104 selects the output of the first phase comparator 101 that performs a linear operation around zero, so that phase synchronization is performed with high accuracy.
The step out detector 106 outputs a step out alarm signal by converting an analog output signal of the second phase comparator 102 to a digital signal. That is, the step out detector 106 outputs the step out alarm signal when the state of phase synchronization is changed to a state where a phase difference between the input signal and the first extracted clock becomes xc2x1xcfx80/2 or more.
However, the conventional PLL has some problems as follows.
For example, in Optical Internetworking Forum (OIF) or International Telecommunications Union (ITU) as standards used in optical communications, the step out alarm signal is defined to be output when the frequency of an extracted clock has drifted by a specified value with respect to the frequency of a reference clock. However, in the PLL based on the conventional art, the step out alarm signal is disadvantageously output at a specific phase difference (xc2x1xcfx80/2 in the conventional example). Therefore, the PLL cannot deal with a given specified value.
It is an object of this invention to obtain a method of and apparatus for detecting a difference between frequencies and a phase locked loop circuit capable of outputting a step out alarm signal when a frequency drift of a given specified value or more between an extracted clock, as an output of a VOC, and a reference clock is detected.
The apparatus for detecting a difference between frequencies according to one aspect of this present invention comprises a beat waveform generating unit which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal, a reference-clock dividing unit which divides the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal, and a frequency comparing unit which compares frequencies of the beat waveform signal and the divided reference-clock signal, and generates a step out alarm signal which is a binary signal depending upon a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal.
The method of detecting a difference between frequencies according to another aspect of this invention comprises generating a beat waveform signal having a frequency which is equal to a difference in frequencies of a reference clock signal and a target clock signal, dividing the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal, and obtaining a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal, and generating a step out alarm signal which is a binary signal depending upon the obtained polarity.
The phase locked loop circuit according to another aspect of this present invention comprises the apparatus for detecting a difference between frequencies according to the present invention.
Other objects and features of this invention will become understood from the following description with reference to the accompanying drawings.